1. Field of the Invention
The present invention relates to acceleration of an address decoding circuit and is preferably applicable in, particularly, a row decoder of a synchronous type high-speed memory.
2. Description of the Prior Art
In a memory apparatus, a row decoder in an address decoding circuit selects one of plural word lines in its memory array according to inputted address signals so as to activate the corresponding memory cells. Thus, an output of the row decoder determines a timing of activation of the memory cells and affects data reading timing in a sense amplifier. Therefore, the acceleration of the address decoding circuit is very important for the acceleration of the memory access.
FIG. 1 shows a conventional address decoding circuit and FIG. 2 shows operating waveform thereof.
This address decoding circuit decodes 7-bit row address signals so as to select a word line 106 from a memory array 100 having 128 rows. The address decoding circuit comprises a predecoding portion 101, a main decoding portion 102, and a word line buffer portion 103. The predecoding portion 101 divides the address signals by 2 bits, 2 bits and 3 bits thereof to decode by using a logical product (AND) gate and outputs predecoded signals of 4 bits, 4 bits and 8 bits. A predecoded signal corresponding to an address of the word line 106 is inputted into an AND gate 104 provided on each of the word lines 106 in a main decoding portion 102 and a decoding result is outputted from the AND gates 104. By executing the decoding through two stages, the decoding is carried out without using a multi-input CMOS so as to achieve the acceleration.
After decoding, the word line buffer 103 activates the word line 106 selected by the main decoding portion 102 by an input of a clock signal. This word line buffer portion 103 activates the word line 106 synchronously with the clock signal by the AND gate in which a decoding result of the main decoding portion 102 and the clock signal are to be inputted. Further, the word line buffer portion is necessary for not activating the memory cells 107 when bit lines of a cell array 100 are precharged. In the word line buffer portion 103, to prevent an occurrence of glitch in the word line 106, the clock signal input timing always must come after the decoding is completed as shown by the operating waveform of FIG. 2.
In such an address decoding circuit, the activation of the word line 106 must be carried out after selection/non-selection of the decoding output is established. Thus, to reduce the decoding time, it is necessary to accelerate both a rise and fall of the decoding output, so that limiting matter for the acceleration increases.
As a solving measure, there is a way in which a precharge type logic is used in a decoding portion 112 as shown in FIG. 3. Because the precharge type logic produces only data transition in a single direction when data is determined, acceleration by adjustment of the size ratio between the P-type MOSFET (field effect transistor) and N-type MOSFET is effective.
In the circuit structure shown in FIG. 3, by obtaining AND between each of an input address and the complementary address and a first clock signal in the address input portion 111, the address signals are converted to signals synchronous to the first clock signal, and in a decoding portion 112, an address signal corresponding to an address of the word line 116 is inputted to a decoding circuit 114 of each word line 116. A decoding circuit 114 is constituted of N-type MOSFETs 117 of the same number as bit width of the address and a P-type MOSFET 118 for precharging. The source terminals of the N-type MOSFETs 117 are commonly grounded and the drain terminals thereof are commonly connected to an output terminal 119. Each of the clock-synchronous address signals is respectively inputted to each gate terminal depending on address of the word line 116. The source terminal of the P-type MOSFET 118 is connected to a power supply level and the drain terminal thereof is connected to the output terminal 119 so that the output terminal 119 is precharged to high level by a precharging signal supplied to a gate terminal thereof. A word line buffer portion 113 obtains AND between each of outputs of the output lines 119 of the decoding portion 112 and a second clock signal so as to output a signal for selecting a word line 116.
While the P-type MOSFET 118 of the decoding portion 112 is turned on by the precharging signal, address inputs to the decoding portion 112 are all set to low level by the first clock signal of the address input portion 111 and the plural N-type MOSFETs 117 of the decoding portion 112 are all turned off so that the output of the decoding circuit 114 is precharged to high level by the P-type MOSFET 118. At this time, the second clock signal of the word line buffer portion 113 remains low level so that the word lines 116 are not activated. If the P-type MOSFET 118 is turned off by the precharging signal and the first clock signal becomes high level so that the address signals are inputted to the decoding portion 112, at least one of seven N-type MOSFETs 117 of each of 127 decoding circuits 114 except the decoding circuit corresponding to the word line 116 indicated by the address is turned on and then the output signal is switched to low level. At this time, in the word line buffer portion 113 of the next stage, the decoded output remains low level even if the second clock signal is inputted. Thus, the word line 116 is not activated. Only an output of the decoding circuit 114 of the word line 116 indicated by the address signal is maintained at a potential at the time of precharge (high level), so that the word line 116 indicated by the address signal is driven by an input of the second clock signal in the word line buffer portion 113 of the next stage.
Because in this address decoding circuit of precharge type, data transition direction (from high level to low level in an example of FIG. 3) in the decoding portion 112 is constant, the decoding circuit 114 has to be accelerated only in a direction in which the word line 116 is turned into non-selective condition (from high level to low level in the example of FIG. 3). Thus, acceleration of the decoding portion 112 is facilitated and adjustment or the like of the size ratio between the P-type MOSFET 118 and N-type MOSFET 117 of each gate is effective.
However, the input timing of the second clock signal in the word line buffer portion 113 must come after it is detected that the word line(s) 116 to be in the non-selective condition should be in the non-selective condition in the decoding circuit 114. Therefore, the second clock signal input timing must be adjusted so as to be later than the decoded signal output like the above-mentioned conventional example.
If the output of the decoding circuit 114 is later than the second clock signal for activating the word line 116, a glitch occurs in the word line 116 thereby leading to malfunction. Thus, the second clock signal for activating the word line 116 must be provided with a sufficient timing margin thereby leading to extending the decoding time. Further, in this example, in the address input portion 111 as well, AND with the first clock signal is obtained due to necessity of converting the input signals to the address decoding circuit to input signals synchronous to the first clock signal and therefore in this portion as well, timing between the address input and first clock signal needs to have a margin. Therefore, the timing margins of these two places may enlarge the decoding time.
As described above, in a conventional synchronous type address decoding circuit for outputting a signal for selectively activating the word line synchronously with the clock signal, irrespective of the predecoding type or precharging type, the clock signal must be inputted after the decoding result of the address signals is established. Thus, there has been provided a timing margin between the establishment of the decoding result and input of the clock signal. However, if the timing margin is too large, the output of the decoding result is delayed so that the operating speed of the address decoding circuit is lowered. On the other hand, if the timing margin is too quick, a glitch occurs in the word line thereby sometimes leading to malfunction. For the reasons, it has been very difficult to set both timings optimally without being affected by various factors of the circuit relating to signal delay.